Analog to digital time base encoder



5 Sheets-Sheet 1 C. L. COHEN ETAL ANALOG TO DIGITAL TIME BASE ENCODER Filed Dec. 29, 1961 Jan. 11, 1966 Jan. 11, 1966 c. L. COHEN ETAL 3,229,272

ANALOG TO DIGITAL TIME BASE ENCODER med Dec. 29, 1961 s sheets-sheet 2 86 FIG. 2

Jan. 11, 1966 c. l.. COHEN ETAL 3,229,272

ANALOG T0 DIGITAL TIME BASE ENCODER Filed Dec. 29, 1961 5 Sheets-Sheet 5 FIG. IO

United States lPatent O von;

Filed nec. 29, 1961, ser. No. 163,356 6 claims. (ci. 3140-347) VThis invention relates generali-.y to :analog parameter to digital information converters .and relates particularly to an analog .to Vdigital time base encoder utilizing pulse height to .time interval conversion.

An instantaneous lstate of a physical system maybe represented yfby an .analog .parameter or by Vdigital information. Illustratively, a state-of a physical system may be the velocitylofa moving object, rthe .analog parameter may `'be .a voltage and the digital :information may be a binary Vnumber or a particular voltage pulse sequence.

An analog to digital converter provides output binary information related yto panticulansequentia'l samples of an input analog tpaiarneter. An analog ztodigita-l time base encoder provides-output pulse gnumerical information from intermediate time .interval information lrelated to the sequential samples.

Tlzhe intermediate .time `interval information .may be obtained by a pulse height to time interval conversion technique. Pulse height to .time .interval :conversion implies that aipulse height related to a sampled value ofan analog parameter is Converted to a representative .time interval.

Azprior art electrical analogrtime base encoder includes means forsampling .analog voltage information periodically, aramp voltage .generator and y.comparison means for establishing a time interval over whichthe ramp voltage reaches the energy level of the .analog voltage sample.

The circuitry thereof is complex and the time `interval i `ing eachsignal is'obtained.

It yis 'the prime 'object of this .invent-ion to provide a pulse height" to time interval vconverter-in which the level of pulse height energy'is utilized tofproduce a ramp `voltage-'whose slope -is related tothe energy'level and in which the time interval is defined bylthe'intersection of the ramp -voltage and a threshold-voltage: level.

It is a second object-of this-invention to 4provide an electricalanalog to digital time base encoder .in which sequential analog voltage samples are utilized to produce respective ramp voltages and the intersection of each ramp voltage with a pre-selected threshold voltage level defines a time interval and the time intervalisquantized by a counter which counts clock pulses duiing the time interval.

It is a third object of this invention to provide an analog to digital converter capable of multiplexing a plurality of analog voltage information signals.

It is a fourth object of this invention to provide .an analog to digital function generator.

.It is a fifth object of thisinvention toy provide` an analog to digital random number generator.

Theforegoing and other. objects, features and advantages of the invention will be apparentfrom the following -more particular description of a preferred embodiment ICC of the invention, as villustrated in the accompanying drawings.

In the drawings:

FIGURE l is a 'block and schematic'diagram f-a circuit suitable for the ypractice of ythis invention;

FIGURES 2 to 9 present waveforms illustrating the manner in which a pulse height is converted Vto Ya corresponding time yinterval by circuitry in accordance with this invention; and

VFIGURE ll0 illustrates the manner in which -a hyper'- bolic function is generated in accordance withthis v.invention.

The analog to .dig-ital time base encoder in accordance with this invention includes means forsampli'ng the 'input analog voltage at particular intervals for providing respective step voltage ypulses. Each voltage pulse height is introduced to an integrator circuit which 'provides a ramp v-oltage whose .slope is representative -offthe voltage pulse height. The integrator circuit has a time vconstant Such that a substantially linear ramp Voltage -is robtained for the duration ofthe Ysampling interval. Therefore, 1the` slope of the ramp voltage is directly proportional'to the amplitude -of Ithe step voltage. Included in the encoder circuitry is a threshold establishing -rneans for lterminating the ramp voltage at a pre-selected voltage lev'l thereby establishing a 'time interval related V'to -the voltage puls height. Circuitry is provided whereby a V counteri'sstated running at the time the analog voltage =-isls`ai`npled. The counter is stopped'when theramp" .voltage reaches 'the preselected threshold value. A clock pulse-source is coupled to the counter and the lnumber of clock pulses counted during the establish-ed `time interval ris the' digital number' whichcorresponds to the magnitude of the'input analog voltage at the sample point.

FIG. l presents a block and schematic diagram of an embodiment -lltlof Athis invention for encoding an analog voltage into a representative digital number.v With'reg'ard tothe block diagram, analog to digital time baseen'c'oder lil comprises analog voltage input terminal 12 and digital information output terminals 14. The analog voltage input terminal l2 isfconnected tothe inputterrninal "16 of scaling circuit v'18. The output terminal 20 'of scaling circuit 18 is connected to the input terminal "22 of sarnpler circuit T24. The output terminal ZGofsainpler circuit 2.4 is connected to the inputterrrii'rial 28 lof pulse-height to time interval converter 0. Theoutputfter'riiial t32 of pulse-height to time interval converter 3i) is connected tothe binary counter 36 via And logic block 401. The output terminal 38 of clock pulse source 4tlfis also connected to And logicblock 401 for incrementing the binary counter 36. Output terminals 44 of'binar'y counter 35 are connected to digital information outputterrnirials $14. Suitable signals for resetting and unloadingthefcounter 236 are appliedto terminal `ftlZby conventional-means'at a time following the closing of And logicblock '401 as `willbe further apparent.

Pulse-height to time interval converter 60 includes start gate circuit path 46, integrator-circuitfpath 48 and threshold selector path 50 which are indicatedrespectively by numbered arrows. Start gate circuit `path .46 includes sta-rt gate circuit 52 Whose input terminal '54 is connected to multivibratorterminal 55 of sampler2`4. The output terminal 56 of start gate circuit S2`is connected tostart gate circuit terminal 5.3 of start-stopcircuit 60. Integrat'or circuit path 43 includesclarnp circuit'6'2` whose input terminal 64 is connected to pulse-height totime converter 30 via inputterrninal 28. Theoutput terminal 5656 of clamp circuit 62 is connected to input terminal 68 Offin- ,tegrator circuit 7). `Outputterminal '72' ofintegrator circuit '70 is connected to .input circuit terminal/ 74 of start-stop circuit '60. Output terminal '76o`f start-stop circuit 60 is connected to output terminal 32 of pulse height to time converter 30.

Threshold selector path 50 includes threshold selector 78 whose input terminal 79 is connected to output terminal 80 of integrator circuit 70. Output terminal 81 of threshold selector 78 is connected to input terminal 82 of start-stop circuit 60.

The block diagram operation of the analog to digital time base encoder of FIG. 1 will be understood through reference to FIGS. 2 to 9. An -analog voltage 86 is applied to analog voltage input terminal 12. Analog voltage 86 has voltage magnitude v(t) vertical axis 88 and occurence time t horizontal axis 90. Analog voltage 86 is introduced to input terminal 16 of scaling circuit 18. Scaling circuit 18f'provides at its output terminal 20 scaled analog voltage 92, FIG. 3, which is related at every point thereofto the respective point of analog voltage 86 by a constant multiplying factor. Scaled analog voltage 92 has voltage magnitude v(t) vertical axis 94 and occurrence time t horizontal axis 96. Scaled analog voltage 92 has maximum voltage V0 indicated by horizontal line 97. Scaled analog voltage 92 is applied to sampler circuit input terminal 22 of sampler circuit 24. Astable multivibrator 84 of sampler circuit 24 provides a sequence of positive going sampling pulses, not shown, whose maximum value is at least as large as V0, FIG. 3. Sampler circuit 24 provides at sampler output terminal 26 the sample voltage pulses 98 of FIG. 4 with voltage axis v* (l) Sample voltage pulses 98 include sequential sample voltage pulses 100 to 107. The leading edge of each sampling pulses from multivibrator 84 actuates start gate circuit 524 which provides av gate pulse which in turn initiates the action of start-stop circuit 60.

Sample volta-ge pulses 98 are clampedto ground by clamp circuit 62 to establish voltage pulse heights 108. Clamp circuit 62 presents at clamp circuit output terminal 6,6 the negative going pulse train 108 of FIG. 5 referenced to ground. The voltage scale for pulse train 108 is v*(t)1 where indicates the variable is already scaled, indicates the variable is sampled, (I) indicates the variable is a function of time, and I indicates that the variable is inverted. Negative going pulse train 108 includes sequential pulses 109 to 116. The leading edge of negative pulse height 109 initiates integrator circuit 70 to provide ramp voltage signal 118. Ramp signal 118 isterminated at threshold voltage level 120. A variable threshold level is selected in a manner described below with reference to FIG. 10 to obtain a binary output linearly related to the analog voltage 86 input. Ramp voltage 122 for negative pulse height 110 is terminated at threshold voltage level 134. Similarly, ramp voltage 125 to 130 related to pulse heights 109 to 116, respectively, are terminated at threshold voltages, not shown.

FIG. 6 illustrates the performance of start gate circuit 52. The leading edge of the multivibrator 84 output pulse corresponding to negative going pulse 109 is introduced to start gate circuit terminal 54 and negative going voltage spike 132 is presented by start gate circuit 52 at its output terminal 56.

FIG. 7 presents the operation of threshold selector 78. Negative going pulse height 109 is introduced to threshold selector 78 on input terminal 79 thereof. Threshold selector 78 presents threshold voltage level 134 on its output terminal 81.

FIG. 8 illustrates in greater detail the nature of and use for the ramp voltage, c g., 118, generated by integrator circuit 70 when a constant threshold voltage level 134 is utilized. Time interval 120 is defined -by the intersection of ramp 118 with threshold level 134. Time interval 124 is defined by the intersection of ramp 122 with threshold level 134.

FIG. 9 illustrates the various output time gates developed by thenegative going pulses and ramp voltages of FIG. 8. Gate pulse 138 exists during time interval 120 and gate pulse 140 exists during the time interval 4 124. Gate pulses 138 and 140 at input terminal 34 of binary counter 36 determine how long it counts for ,the corresponding pulse heights 109 and 110.

FIG. 10 illustrates the manner in which a constant threshold voltage level for each ramp voltage associated with a sample pulse causes a hyperbolic function to be provided on digital information output terminal 14 of encoder 10, FIG. l. It also illustrates how a variable threshold voltage level in accordance' with a hyperbolic function causes encoder 10 to provide a Binary output on terminal 14 which linearly related to the analog voltd age 86 on input terminal 12. The vertical axis 88 is the magnitude v(t) of the analog voltage while the horid zontal axis 90 is time t. Illustrative ramp voltages 149 to 149 establish progressively longer time intervals from the time axis 90 origin and correspond respectively to progressively greater energy levels of the input analog voltage 86, i.e., they do correspond to the particular negative pulse heights of FIG. 5. Ramp voltage to 147 intersect threshold voltage 134 at points 151 to 158, respectively. The intersections of ramp voltages 159 and 160 with threshold voltage level 134 are not shown as their locations are oif the drawing. It is apparent that the corresponding time intervals from the origin of the time axis`90 for points 151 to 158 increase in valve respectively. It can be shown that this increase is a hyperbolic function given by the expression I=K/ V, where t=time, K=threshold voltage in volts times the RC time constant of integrator circuit 70 and V is the amplitude of the sample pulse height in volts. If the horizontal-threshold :voltage 134 is replaced by a threshold voltage level which follows curve 162, the time intervals between adjacent intersections 151, 152 and 163 to 170 are of equal value. i

It will be readily apparent to one skilled in the art that various functions can be obtained by varying the nature of the threshold voltage curve 162. For those curves 162 which have a particular geometrical conguration, the output sequences will be specifically determined mathematically. However, if a particular time sequence is desired which can not be represented by a linear function, then the nature of curve 162 is readily determined by experiment. Encoder 10, FIG. 1, is a random nurnber generator if the voltage input on input terminal 12 has random values. v

The yparticular circuits utilized for a preferred ernbodiment of this invention will 'be desc-ribed with respect to the schematic diagram o-fFIG'. l. Scaling circuit 18 includes resistors 200 and 202 and operational amplifier 204. One end of resistor 200 is connected between input terminal 16 and input terminal 206 of operational arn-l plifier 204. Resistor 202 is connected between input terminal 206 of operational amplifier 204 and output terminal 20 of scaling circuit 18. The operational ampliter 204 of scaling circuit 18 has ascaling factor Rs/Rin where Rin is resistor 200 and Rs is resistor 202.

Sampler circuit 24 has its input terminal 22 connected to the anode 210 of diode 212 whose cathode is connected to sampler output terminal 26. Resistor 216 is connected between terminal 26 and negative voltage source -V1. Output terminal 55 of astable multivibrator is connected to anode 222 of diode 224. Cathode 226 of diode 224 is connected to output terminal 26 of sampler circuit 24. Analog voltage 86, FIG. 2, applied to scaling circuit 18 on its input terminal 16 is scaled to scaled analog voltage 92, FIG. 3. Through the use of scaling cir-cuit 18, it is possible to scale the input analog voltage 86 up or down in -accordance with the capacity of the ensuing circuitry. Multivibrator 84 produce nega tive going sequential pulses, not shown, whose magnitude'Y must be suicient to sample the greatest negative going excursion of the analog voltage. Diodes 212 and 224 comprises an AND circuit whose output follows the most positive voltage applied thereto. Thus, the output pulses,

134. The 'junction of capacitor 226 Iand diode `230 is clamp lcircuit output terminal 66. clamps sampled analog voltages 980i FIG. 4to ground land *establishes y-pulse Iheights 1108, FIG. -5.

Clamp circuit 62 Integrator circuit 70 includes isolation portion 236 and `integrator `portion 238. Isolation :portion 236'comprises `NPN transistor '240 whose base 242 is connectedvtoclamp circuit 'output terminal 66 land whosecollector 244 iis connected -to'positive voltage source -l-V2. lEmitter 248 of transis- 'tor-'240is connectedfto base 250of NPN transistor 252. 'Collector E254 of transistor 252 isconnected `to :positive voltage source ,il-V2 and emitter 12S6fthereof isconnected to integrator circuit threshold selector terminal 80. Resistor 258 is connected `:between emitter 256 to negative Voltage source -V3. Isolation circuit 236 is an impedance matcher and lpermits integratonportion 238 to integrate veach "pulse vheight applied thereto Without loading downthe previous circuitry.

Integrator portion 238 includesresistor262 connected between terminal 80Vand integrator circuit output terminal 72. -Capa'citor264is `connected between terminal 72 and-ground 1"34. lIntegrator portion 238 is an RC integrating network which provides a ramp voltage output for a step voltage input.

Start-stop circuit 60 includes PNP transistors 266 and 268. Base 270 of transistor 266 is connected to start-stop circuit input terminal 74 and base 272 of transistor 268 is connected to output terminal 76 via capacitor 280. Collectors 274 and 275 of transistors 266 and 268 are connected to negative voltage source -V4 via resistors 276 and 278, respectively. Collector 274 of transistor 276 is connected to source -l-VS by way of clamping diode 400. Input terminal 74 is connected to diode 288 via capacitor 286. Collector 274 of transistor 266 is also connected via the series path of capacitor 280 and resistor 282 to emitter 284 of transistor 268. Emitter 284 is connected to ground 134. Collector 275 of transistor 268 is also connected via diode 288 to positive voltage source -l-VS. Start-stop circuit input terminal 58 is connected to the base 272 of transistor 268. Diode 294 is connected between base 272 and emitter 284 of transistor 268. Its anode 296 is connected to the base 272 and its cathode 298 is connected to the emitter 284.

Start gate circuit 52 includes capacitor 300 connected to start gate circuit input terminal 54 and junction 302. Resistor 304 is connected between junction 302 and ground 134. Variable capacitor 324 is connected between junction 302 and the anode 310 thereof is connected to start gate circuit output terminal 56.

Stop threshold selector circuit 78 includes the series path of variable resistors 312 and 314 connected between threshold selector input terminal 79 and the base 316 of PNP transistor 318. Variable capacitor 320 is connected between the junction 322 of resistors 312 and 314 and ground 134, Variable capacitor 324 is connected between the base 316 of transistor 318 and ground 134. Ernitter 326 of transistor 318 is connected to ground 134 and the collector 328 thereof is connected via variable resistor 330 negative voltage source -V6. Collector 330 is also connected to threshold selector output terminal 81.

Certain aspects of the nperation of the analog to digital time base encoder of FIG. 1 will now be described in greater detail. The start gate circuit 52 differentiates the waveform from multivibrator 84 thereby producing a negative gate pulse which causes transistor 268 of startstop circuit 60 to turn on. This initiates the running of binary counter 36 which counts the clock pulses from clock pulse source 40. The input to integrator portion 238 is also fed into threshold selector '76 which establishes an approximate hyperbolic waveform at its output terminal 81. Through adjustment of the variable resistors and variable` capacitors of thresholdselector 78 lit generates the approximate 1hyperbolic waveform.

Transistor 268 4of start-'stop circui-t 60 continues to conduct =until the `ramp voltage `at input terminal 74 of startstop circuit 60 is just slightly negative with respect -to the lapproximate hyperbolic function waveform from threshold selector 78 at its input terminal 82. At this time transistor 266lofrstart-stopcircuit'60turns on andthe change in `v'oltage'at its collector-274 turns'ol the binary counter 36. Transistor 268 is turnedolf *by feedback action via 1capacitor 280 land resistor 282.

VAs result of the foregoing operation, binary counter 36 contains a digital number representative o'f the time finterval related to the sample pulse vheight yof vthe =irput 'analog voltage.

While the invention has been particularly shown and Edescribed with reference-to a preferred'embodiment thereof, 4it'will -be #understood fby those skilled in the art that `vvarious changes'in form and'details may 1be made therein 'without'departing'fr'om the spirit'and scope :of the =inven tion.

What is-claime'd yis: 1. A signal amplitude to time conversion means comprising:

#means to receive an input signal for conversion;

meansfor :providing a referencefsignal-ofknown amplitude;

comparator means for subtracting the amplitude of said input signal from said reference signal so that a relatively large signal amplitude provides a relatively small signal level in the output thereof and a relatively small signal amplitude provides a relatively large signal level in the output thereof;

integrator means for generating a ramp signal having a slope which is related to the signal level applied thereto by said subtracting means;

threshold generating means for generating a signal level representative of the amplitude :of said input signal;

detectormeans responsive to the ramp output of said integrator means and to said threshold level signal to detect when said ramp integrator output signal bears a preselected relationship with said threshold level signal;

means responsive to said detecting means for measuring the time required for said ramp signal from said integrator means to reach said preselected relationship representing the time conversion of said input signal applied to said subtracting means.

2. Conversion means according to claim 1 wherein:

said threshold signal generating means generates a signal level to provide a linear relationship between the amplitude of said input signal and the time required for said ramp signal of said integrator means to reach said preselected relationship.

3. Conversion means according to claim 1 wherein:

said threshold signal generating means generates a signal level to provide a nonlinear relationship between the amplitude of said input signal and the time required for said ramp signal of said integrator means to reach said preselected relationship.

4. An analog to digital conversion system comprising:

means to receive an analog input signal varying in time for conversion;

a sampling gate source:

a sampling means responsive to said sampling gate source and said means to receive an analog input signal for sampling the amplitude of said input Signal;

a binary counter;

a relatively high frequency clock pulse source;

start-stop gating means electronically disposed between said relatively high frequency clock pulse source and said binary counter;

said start-stop gating means being responsive to said samplinggate source so as to initiate the counting of said relatively high frequency clock pulses in said binary counter in response to the leading edge of the signal output of said sampling gate;

a signal amplitude-tO-time conversion means comprising:

means for providing a reference signal of known amplitude;

means for subtracting the amplitude of said input signal from said reference signal so that a relatively large signal amplitude provides-a relatively small signal level in the output thereof and a relatively small signal amplitude provides a relatively large signal level in the output thereof;

integrator means for generating a ramp signal having a slope which is related to the signal level applied thereto by said subtracting means;

threshold generating means for generating a signal level representative of the amplitude of said input signal;

a detector means responsive to the ramp output of said integrator means and to said threshold level signal to detect when said integrated output signal bears a preselected relationship with said threshold signal level;

means responsive to said detecting means for generati ing a stop signal for application to said start-stop gating means for the purpose of stopping the application of said relatively high frequency clock pulses to said binary counter such that the number stored in said counter is representative of the amplitude of said input signal.

5. A conversion system accord-ing to claim 4 wherein said means supplying the threshold signal comprises:

said means for supplying the threshold signal comprises:

electronic means for deriving a preselected non-linear relationship between the amplitude of the output signal of said sampling means and the time required for the amplitude of said ramp signal of said integrator means to reach said preselected relationship.

References Cited by the Examiner UNITED STATES PATENTS 2,897,486 7/1959 Alexander et al. 340--347 2,963,697 12/1960 Giel 340-347 25 MALCOLM A. MORRISON, Primm Examiner.

D. M. ROSEN, L. w. MAssEY, K. R. STEVENS,

Assistant Examiners. 

1. A SIGNAL AMPLITUDE TO TIME CONVERSION MEANS COMPRISING: MEANS TO RECEIVE AN INPUT SIGNAL FOR CONVERSION; MEANS FOR PROVIDING A REFERENCE SIGNAL OF KNOWN AMPLITUDE; COMPARATOR MEANS FOR SUBTRACTING THE AMPLITUDE OF SAID INPUT SIGNAL FROM SAID REFERENCE SIGNAL SO THAT A RELATIVELY LARGE SIGNAL AMPLITUDE PROVIDES A RELATIVELY SMALL SIGNAL LEVEL IN THE OUTPUT THEREOF AND A RELATIVELY SMALL SIGNAL AMPLITUDE PROVIDES A RELATIVELY LARGE SIGNAL LEVEL IN THE OUTPUT THEREOF; INTEGRATOR MEANS FOR GENERATING A RAMP SIGNAL HAVING A SLOPE WHICH IS RELATED TO THE SIGNAL LEVEL APPLIED THERETO BY SAID SUBTRACTING MEANS; THRESHOLD GENERATING MEANS FOR GENERATING A SIGNAL LEVEL REPRESENTATIVE OF THE AMPLITUDE OF SAID INPUT SIGNAL; DETECTOR MEANS RESPONSIVE TO THE RAMP OUTPUT OF SAID INTEGRATOR MEANS AND TO SAID THRESHOLD LEVEL SIGNAL TO DETECT WHEN SAID RAMP INTEGRATOR OUTPUT SIGNAL BEARS A PRESELECTED RELATIONSHIP WITH SAID THRESHOLD LEVEL SIGNAL; MEANS RESPONSIVE TO SAID DETECTING MEANS FOR MEASURING THE TIME REQUIRED FOR SAID RAMP SIGNAL FROM SAID INTEGRATOR MEANS TO REACH SAID PRESELECTED RELATIONSHIP REPRESENTING THE TIME CONVERSION OF SAID INPUT SIGNAL APPLIED TO SAID SUBTRACTING MEANS. 